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Test Under Mask Hardware

IP.com Disclosure Number: IPCOM000088410D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Boggs, JK: AUTHOR

Abstract

In a microprogrammed data processor, a series of microcode steps are required to determine the condition code setting for the TEST UNDER MASK (TM) machine instruction. The hardware described herein automatically determines the condition code setting for this type of instruction. This enables a significant reduction in overall instruction execution time

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Test Under Mask Hardware

In a microprogrammed data processor, a series of microcode steps are required to determine the condition code setting for the TEST UNDER MASK (TM) machine instruction. The hardware described herein automatically determines the condition code setting for this type of instruction. This enables a significant reduction in overall instruction execution time

The TEST UNDER MASK instruction is of the storage-immediate (SI) type. The "immediate" byte of data (bits 8 - 15 of the instruction) is used as an eight-bit mask. The mask bits correspond one-for-one with the eight bits in the storage location specified by the operand address in the instruction. A mask bit value of one indicates that the respective bit in storage is to be tested. When the mask bit is zero, the storage bit is ignored. When all selected storage bits are zero or if the mask is all zeros, the condition code (CC) is set to zero. When the selected storage bits are all ones, the condition code is set to three. Any other combination (mixed) results in a condition code of one.

Fig. 1 shows the hardware for performing the test. M0, M1,...,M7 denote the mask bits, and S0, S1,...,S7 denote the storage bits. A set of eight test circuits, collectively identified by reference numeral 10, individually receive one of the mask bits and the corresponding one of the storage bits. Each of these test circuits is of the same construction, the construction of the Test 0 circuit being shown in detail in Fig. 2. The A0 output has a value of 1 if storage bit S0 is being tested (M0 = 1) and S0 is 1 or if storage bi...