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Browse Prior Art Database

Logic Block Coincident Circuit

IP.com Disclosure Number: IPCOM000088441D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR

Abstract

Fig. 1 shows cell circuitry for providing the AND-OR-INVERT (AOI) function. When circuitry 2 is deleted therefrom, the AND-INVERT (AI) function is obtained. Using these gates, the coincidence function may be produced in 2 cells, as illustrated in Fig. 2. When A and B are logical "1"s, cell S1 provides a logical "0" output forcing the output of S2 TO a "1". When A and B are logical "O"s, the output of S2 is a logical "1". This is the desired coincidence function.

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Logic Block Coincident Circuit

Fig. 1 shows cell circuitry for providing the AND-OR-INVERT (AOI) function. When circuitry 2 is deleted therefrom, the AND-INVERT (AI) function is obtained. Using these gates, the coincidence function may be produced in 2 cells, as illustrated in Fig. 2. When A and B are logical "1"s, cell S1 provides a logical "0" output forcing the output of S2 TO a "1". When A and B are logical "O"s, the output of S2 is a logical "1". This is the desired coincidence function.

Fig. 3 discloses the interconnection of two of the AND-OR-INVERT cells of Fig. 1 to provide the exclusive-OR function.

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