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Schottky Transistor Logic Base Extension Cell

IP.com Disclosure Number: IPCOM000088445D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Chen, JZ: AUTHOR [+5]

Abstract

This article describes a cell that provides full accessibility to the base at first metal level with additional accessibility to all vertical wiring channels within the cell.

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Schottky Transistor Logic Base Extension Cell

This article describes a cell that provides full accessibility to the base at first metal level with additional accessibility to all vertical wiring channels within the cell.

This provides increased wireability since the input to the base can be wired using first level metal only.

Reference is made to the circuit schematic (Fig. 1) and the cell layout (Fig.
2). A base extension into the wiring region is achieved by structuring an underpass resistor in series with the resistor R1. The resistance value of the underpass resistor is very small relative to that of R1. Thus, it does not impact circuit performance.

The cell includes the underpass resistor. The underpass resistor has multiple Logic Service Terminals (LSTs) defined on the wiring grid. A connection to the base of the NPN transistor is made by wiring nets from Schottky outputs to an available underpass LST position. The base is connected to the underpass resistor by fixed metal connection A. The underpass resistor is fabricated by a standard bipolar process.

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