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High Performance Bipolar P MOS Logic Switching Circuit

IP.com Disclosure Number: IPCOM000088446D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Perris, J: AUTHOR [+2]

Abstract

The bipolar P-MOS (metal oxide semiconductor) logic gate utilizes a minimal area and at the same time provides sound performance characteristics.

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High Performance Bipolar P MOS Logic Switching Circuit

The bipolar P-MOS (metal oxide semiconductor) logic gate utilizes a minimal area and at the same time provides sound performance characteristics.

In Fig. 1, a P-MOS field-effect transistor (FET) 10 serves as a load resistor for Schottky barrier diode (SBD)-clamped transistors 12, 13, 14, 15 which are operated in the normal mode. A PN junction diode 11 provides level shifting for FET 10. Resistors 01, 02, 03, 04 are used in series with the input lead to the bases of transistors 12, 13, 14, 15 to avoid current-hogging problems.

The vertical cross sectional view of the devices is depicted in Fig. 2.

The following process steps may be employed: 1) collector V-EPI (epitaxial) growth 2) etch for ROI (recessed oxide isolation) 3) ROI deposition 4) etch ROI wall for FET 5) N-EPI growth for FET 6) base, emitter and contact diffusions 7) glass oxide deposition 8) etch for thin oxide FET gate 9) contact opening and metallization.

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