Browse Prior Art Database

Slotted Macro Design Structure

IP.com Disclosure Number: IPCOM000088447D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Fox, BC: AUTHOR [+5]

Abstract

The future direction of large-scale integration (LSI) will be one of increasing density on chips. The integrated injection logic (I/2/L) technology offers density improvements over transistor-transistor logic (T/2/L) bipolar. This density trend can't be continued using the conventional unit logic masterslice (MS) approach because the density would be limited by the wiring required to interconnect unit logic cells. As such, there will be a need to go forward with an I/2/L macro design philosophy whether it be macro on MS and/or macro on a custom chip. One problem with the I/2/L macro design is that the intramacro wiring tends to be packed to achieve density. As such, the global wiring (intermacro to macro wiring) connections will be elongated because they have to go around the macro.

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Slotted Macro Design Structure

The future direction of large-scale integration (LSI) will be one of increasing density on chips. The integrated injection logic (I/2/L) technology offers density improvements over transistor-transistor logic (T/2/L) bipolar. This density trend can't be continued using the conventional unit logic masterslice (MS) approach because the density would be limited by the wiring required to interconnect unit logic cells. As such, there will be a need to go forward with an I/2/L macro design philosophy whether it be macro on MS and/or macro on a custom chip. One problem with the I/2/L macro design is that the intramacro wiring tends to be packed to achieve density. As such, the global wiring (intermacro to macro wiring) connections will be elongated because they have to go around the macro. Arbitrary allotment of silicon space within a macro for global wiring will be inefficient because that would require too much space to satisfy a random connect situation. A random global connect implementation requires approximately two-thirds of the chip area. In addition, the macro logic service terminals (LSTs) might not be ideally located, which would tend to increase global connection lengths. Either of the above cases would impact the density. This article describes a slotted macro design structure for I/2/L that will minimize the global wiring area of silicon, and thereby provide improved chip density.

Given a macro of size M x N circuits (Fig. 1) spanning X and Y horizontal and vertical channels, respectively, a global wiring assessment indicates that the macro should be subdivided to allow global X(G) and Y(G) wires to feed through the macro. As such, the macro implementation would be as shown in Fig. 2, where M1 + M2 = M circuits, N1 + N2 = N circuits, X1 + X2 = X horizontal channels, Y1 + Y2 = Y vertical channels, XG = horizontal channels required for global interconnect, and YG = vertical channels required for global interconnect.

The example s...