Browse Prior Art Database

Double Pulse Generation

IP.com Disclosure Number: IPCOM000088453D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Grunbok, WW: AUTHOR [+2]

Abstract

Sequential pulse pairs are generated using only one delay circuit and, hence, minimum hardware. This circuit can be used for driving clocked logic modules, such as programmed logic circuits.

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Double Pulse Generation

Sequential pulse pairs are generated using only one delay circuit and, hence, minimum hardware. This circuit can be used for driving clocked logic modules, such as programmed logic circuits.

The circuit of Fig. 1 produces a pair of closely spaced pulses on outputs 1 and 2 in response to each input pulse on line 3, using only a single time delay (TD) circuit 4. Each input pulse triggers waveform A of Fig. 2 at the output of AND inverter (AI) 5, which then triggers waveform B at the output of AI 6. Waveform B, in turn, initiates the first output pulse of waveform E via line 7 and AI 8 and also initiates the second output pulse of waveform C via AI 9 and TD circuit 4. Waveform C terminates the pulse of output waveform E.

Waveform C also is fed back via line 12 to cross-connected AI 10 and AI 11 to generate waveform D which terminates the pulse of waveform A via AI 5. The termination of the waveform A pulse terminates the pulse of waveform B and, after the delay of AI 9 and TD circuit 4, also terminates the pulse of output waveform C.

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