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LSSD Latch Configuration which Requires fewer Input Changes for both Scan In and Scan Out Operation

IP.com Disclosure Number: IPCOM000088480D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Lee, DE: AUTHOR

Abstract

This level-sensitive scan design (LSSD) latch uses a master-slave pair which requires no clock inversion and sets on opposite phases of the clock, allowing a single clock to control the shift function of the latch. The latch configuration reduces the number of input changes to perform the Scan In/Out function and correspondingly the number of test patterns when employed in an LSSD test system. Reference is made to U. S. Patents 3,761,695; 3,783,254; and 3,784,907.

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LSSD Latch Configuration which Requires fewer Input Changes for both Scan In and Scan Out Operation

This level-sensitive scan design (LSSD) latch uses a master-slave pair which requires no clock inversion and sets on opposite phases of the clock, allowing a single clock to control the shift function of the latch. The latch configuration reduces the number of input changes to perform the Scan In/Out function and correspondingly the number of test patterns when employed in an LSSD test system. Reference is made to U. S. Patents 3,761,695; 3,783,254; and 3,784,907.

Referring to Fig. 1, Scan is the LSSD clock and Data and Data* are the LSSD shifted inputs. Clock 1 and Clock 2 are the system clocks. Under normal operation Scan is held low and the latch operates as a normal master-slave pair under the control of Clock 1 and Clock 2. When data is to be scanned in and out of the latch, Clock 1 and Clock 2, are held low. When Scan is brought high, Data and Data* are shifted into FM*/FM. When Scan is brought low, FM*/FM is scanned into FS/FS*. The data has been shifted through both the master and the slave with only two input changes.

A race condition does exist in this configuration. When Scan is brought high, device #1 or #2 will be turned on. This transition must not affect the state of the latch FS/FS* to avoid this race. If the transition at Scan is very fast (faster than a minimum circuit delay), the latch FS/FS* will be turned off before signal changes at FM or FM* can affect the FS/FS* latch.

When Scan falls, FS or FS* will be forced high, and this must not...