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Doped Polysilicon Diffusion Source for Self Aligned Gate Field Effect Transistor

IP.com Disclosure Number: IPCOM000088483D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Huang, PC: AUTHOR [+2]

Abstract

A doped polysilicon diffusion source in combination with a 300 Angstrom silicon nitride mask for gate regions provides shallow junction depths of less than one micron, short channel lengths of the order of 2.5 microns and threshold voltages of the order of 1.1 to 2 volts in P- type substrates having a resistivity of 1.3 to 1.7 ohm-centimeters. A process incorporating these features achieves a substantially planar surface for metallurgy with improved wiring density.

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Doped Polysilicon Diffusion Source for Self Aligned Gate Field Effect Transistor

A doped polysilicon diffusion source in combination with a 300 Angstrom silicon nitride mask for gate regions provides shallow junction depths of less than one micron, short channel lengths of the order of 2.5 microns and threshold voltages of the order of 1.1 to 2 volts in P- type substrates having a resistivity of
1.3 to 1.7 ohm-centimeters. A process incorporating these features achieves a substantially planar surface for metallurgy with improved wiring density.

In Fig. 1A a 6000 Angstrom silicon dioxide layer 10 is formed on P- type silicon substrate 12 with [100] crystal orientation. An opening 14 is appropriately formed in the layer 10 as the gate region for a subsequent FET device. A layer of silicon nitride 16 is appropriately deposited to form on the layer 10 and on the substrate 12, as shown in Fig. 1B. Appropriate masking and etching takes place on the layers 10 and 16 to form source 18 and drain 20 areas, as shown in Fig. 1C. A layer of highly doped N type polysilicon 22 is formed across the surface of the layer 16 and in the areas 18 and 20 by conventional processes. Layer 20 is formed to a thickness of the order of 3000 Angstrom.

In Fig. 1D drive-in and reoxidation of the layer 22 occurs to form N+ source and drains about the areas 18 and 20. A photoresist layer 24 is appropriately formed on the polysilicon to redefine the layer 16 by etching in hydrochloric acid to rem...