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Cache Address Directory Invalidation Scheme for Multiprocessing System

IP.com Disclosure Number: IPCOM000088496D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Jones, JD: AUTHOR [+2]

Abstract

This article describes how cache directory fetches or invalidations may be performed in a four-way multiprocessing (MP) system without drastically affecting throughput.

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Cache Address Directory Invalidation Scheme for Multiprocessing System

This article describes how cache directory fetches or invalidations may be performed in a four-way multiprocessing (MP) system without drastically affecting throughput.

Registers 10 are added to the central processing unit (CPU) to hold pending invalidation requests. Comparators 12 are added to compare the contents of the registers 10 with the translated address and the directory design 14 is modified to allow two accesses in the same Processor Storage Control Function (PSCF) cycle. Assuming that remote and local invalidation requests come into a PSCF at a one-cycle rate and an invalidation request takes one PSCF cycle, then the following could be accomplished. 1. CPU directory requests will be accomplished in 1/2 PSCF cycle. 2. Invalidate directory requests will be accomplished in 1/2 PSCF cycle.

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If during the invalidate cycle it is found that an entry is in the directory 12, pending PSCF directory requests will not be accepted for one cycle and the entry will be invalidate during what would have been a PSCF directory half cycle.

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If during a CPU directory cycle a cache fetch request is initiated and the translated address being fetched is the same as an address to be invalidated on the next 1/2 cycle, the data must not be fetched from the cache. If the data were allowed to be fetched, it might not represent the most current data. Therefore, a compare must be ma...