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Delay Testing and Diagnosis of LSSD Shift Register Strings

IP.com Disclosure Number: IPCOM000088503D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 6 page(s) / 135K

Publishing Venue

IBM

Related People

Dimitri, KE: AUTHOR

Abstract

This is a description of a technique for generating a minimum set of patterns that could be used for both testing and diagnosing delay faults of the shift portion of a level sensitive scan design (LSSD) shift register string and its shift clock drivers.

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Delay Testing and Diagnosis of LSSD Shift Register Strings

This is a description of a technique for generating a minimum set of patterns that could be used for both testing and diagnosing delay faults of the shift portion of a level sensitive scan design (LSSD) shift register string and its shift clock drivers.

Fig. 1 shows the test pattern circuit. It consists of a shift register string of three shift register latches (SRLs) and shift clock drivers A and B.

Delay fault test patterns for any SRL in a shift register string are based on two basic tests. The first test is the minimum latch up (MLU) test. It defines the minimum time between the change in state of a data line and the turning off edge of the clock signal so that the latch results in latching the last data value change ("1" or "0"). The second test is the nonpropagating pulse (NPP) test. It determines the minimum time between the turning off edge of the clock signal and the earliest change in state of the data line so that the latch results in an undisturbed state. The first and second tests are shown in Figs. 3 and 4 respectively.

As shown in Fig. 2, each SRL consists of two latches, L1 and L2. Each latch is tested with four test patterns as follows: MLU test for a logical "1" data MLU test for a logical "0" data NPP test for a logical "1" data NPP test for a logical "0" data

Table 3 shows the derivation of any MLU or NPP test for any nth SRL position in a shift register string (first SRL closest to scan-in). Table 1 and Fig. 2 show how these tests and their subpatterns are generated for the second SRL of the test circuit.

The DC string setup sets the state value of the SRL logic preceding (position wise) the latch for which the test is being generated. This logic state will allow the scan-in of that latch to change state (analogou...