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Browse Prior Art Database

Interrupt Stacking

IP.com Disclosure Number: IPCOM000088510D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 53K

Publishing Venue

IBM

Related People

Draper, WD: AUTHOR [+4]

Abstract

In many current program-controlled processors, particularly communication processors, each interrupt service request must be processed before I/O operations of the chain may continue. This article describes a technique which permits multiple interrupts to be stacked and processed together. The described interrupt stacking capability also substantially eliminates overrun potential between interrupts and substantially improves the performance of the processor. With the described technique wideband communication facilities are more easily supported.

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Interrupt Stacking

In many current program-controlled processors, particularly communication processors, each interrupt service request must be processed before I/O operations of the chain may continue. This article describes a technique which permits multiple interrupts to be stacked and processed together. The described interrupt stacking capability also substantially eliminates overrun potential between interrupts and substantially improves the performance of the processor. With the described technique wideband communication facilities are more easily supported.

The key element in providing the above capability is the use of a Process Control Block (PCB) having the format shown in Fig. 1. Among other information, the PCB contains the address of the next PCB in a chain of PCBs and an Interrupt Service Request (ISRS) field which, in the case of the first PCB of a data block, points to the PCB containing the data block status or to the PCB containing a Program-Controlled Interrupt (PCI).

Fig. 2 illustrates a sample PCB chain for a receive operation.

The Control Program (CP) prepares a chain of PCBs (nine in the example) and issues a start I/O to the hardware for a particular line or channel with a pointer to PCB 1. The CP may now service other lines, do background processing, etc., until an interrupt is issued for this line.

The hardware accepts the start I/O, saves the pointer to PCB 1, obtains (via cycle steal) control information associated with PCB 1 and monitors the line for the start of a data block. When data is received, the hardware moves the data (via cycle steal) to processor storage at the location specified in the PCB data field. When the data area is full (indicated by PCB length field), PCB 1 is marked complete and the "Next PCB" pointer is used to locate PCB 2. Data transfer continues using PCB 2 until an ending status is recognized, such as either the data area is full or an end of message flag is detected. If an end flag is detected, then the hardware sets final status for the block in PCB 2, stores PCB 2's Address in the ISRS field of PCB 1, obtains PCB 3's address from PCB 2's "Next PCB" pointer and sets an interrupt service request.

n interrupt service request will cause an interrupt to the line service code in the processor when the interrupt level is available and no other higher level interrupt service requests are pending. Note, processing of an interrupt service request may be delayed as long as "higher priority" work exists for the processor. During this time, the hardware continues to process the PCB chain.

Block two transmitted on the line happens to be small enough to be contained in the data area associated with PCB 3 so final status for block two is placed in PCB 3. The hardware then stores PCB 3's address in its own ISRS field, obtains PCB 4's address and sets an interrupt service request.

In this example, the interrupt service request for block one has not been honored yet so the second request do...