Browse Prior Art Database

Initialization Signal Generation

IP.com Disclosure Number: IPCOM000088513D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 61K

Publishing Venue

IBM

Related People

Peterson, RA: AUTHOR

Abstract

Functional units of a computer system must be initialized when power is applied to the system. In order to save cost, and particularly where the functional units are designed with large-scale integrated (LSI) circuitry, it is not desirable to include initialization signal generating circuitry which is solely used for that function. The initialization signal generating circuitry can be formed from latches having data inputs which are not simultaneously active during normal operation of 1 the functional unit. The latches in the functional unit meeting this criteria can then be interconnected for scan-in operations where each latch is set to the same state, and this condition is decoded to generate the initialization signal.

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Initialization Signal Generation

Functional units of a computer system must be initialized when power is applied to the system. In order to save cost, and particularly where the functional units are designed with large-scale integrated (LSI) circuitry, it is not desirable to include initialization signal generating circuitry which is solely used for that function. The initialization signal generating circuitry can be formed from latches having data inputs which are not simultaneously active during normal operation of 1 the functional unit. The latches in the functional unit meeting this criteria can then be interconnected for scan-in operations where each latch is set to the same state, and this condition is decoded to generate the initialization signal. The initialization signal is terminated by allowing the data inputs of these latches to be active, because, by definition, the decode will no longer be satisfied; i.e., the outputs from this particular group of latches are no longer all in the same state.

The latches in Fig. 1 are of the type having a scan-in input and a data input, as shown in Fig. 2 and set forth in U.S. Patent 3,806,891. These latches are representative of latches in an adapter for a disk storage drive, for example. Of the latches shown, latches 10 have data inputs which are never all at the same state simultaneously during normal operation. Latches 11 and 12 could be set to the same state during their normal operation.

The adapter, which includes a data storage buffer (not shown), must be initialized; i.e., the latches therein are initially reset and the buffer is initialized so as to provide good parity and valid system channel pointer values in selected locations. The initialization function for the buffer is performed by LSI chip 20. The initialization signal for chip 20, however, is generated by decoding the states of latches 10, which are all set to a one state d...