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Browse Prior Art Database

Microinterrupt via Forced Branch and Link Instruction

IP.com Disclosure Number: IPCOM000088514D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 70K

Publishing Venue

IBM

Related People

Booth, RC: AUTHOR [+2]

Abstract

Interrupt capability is added to a microprocessor by providing controls which inhibit storage selection during the current instruction Fetch (I-Fetch), inhibit increment of the instruction address register (IAR), force a Branch and Link (BAL) instruction, force certain bits in the storage address register (SAR) to zero, reset the microinterrupt request and save the contents of the program condition register (PCR).

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Microinterrupt via Forced Branch and Link Instruction

Interrupt capability is added to a microprocessor by providing controls which inhibit storage selection during the current instruction Fetch (I-Fetch), inhibit increment of the instruction address register (IAR), force a Branch and Link (BAL) instruction, force certain bits in the storage address register (SAR) to zero, reset the microinterrupt request and save the contents of the program condition register (PCR).

The microprocessor (Fig. 1) processes microinstructions in one or two cycles. The microinstructions are fetched from storage 10 in a manner where the next microinstruction is fetched during the execution of the current instruction. This overlapped operation, as well as the number of T-times per cycle, is illustrated in Fig. 2. Instruction X+l is being executed while Instruction X+2 is fetched from storage.

The instructions fetched from storage 10 are entered into operation (OP) register 15, where bits 0-2 define the instruction mode. Storage Read and Write instructions require two cycles and are modes 4 and 5, respectively. Modes 6 and 7 are for branch instructions, mode 3 is for I/O instructions, and modes 0, 1 and 2 are for arithmetic and logical instructions. In this instance the source of the interrupt condition comes from an I/O adapter connecting an I/O device (not shown) to the microprocessor (Fig. 3).

The adapter interrupt condition is stored in polarity-hold circuit 50 at T11 time. The output of circuit 50 is an Interrupt Request signal, which is applied to AND Circuit 21, together with signals indicative of whether or not a Mode 4-7 instruction is being executed, and whether or not a Mode 5 second cycle signal is active. AND Circuit 21 passes a signal to set microinterrupt-detected trigger 22 at ring 3...