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Adaptive Equalizer for Read Channel

IP.com Disclosure Number: IPCOM000088522D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Comstock, RL: AUTHOR [+2]

Abstract

As shown in Fig. 1, an adaptive equalization circuit 1 between preamplifier 2 and AGC circuit 3 of a read channel employs differential sum slimming of both leading and trailing edges. The preamplified readback pulse is differentiated and scaled by a factor A in circuit 4. The output of circuit 4 is then summed with the readback pulse in junction 5 to slim the trailing edge. Similarly, the output of junction 5 is differentiated and scaled by a factor B in circuit 6, the output of which is summed with the input in junction 7 to slim the leading edge. The factors A and B are controlled adaptively in order to produce slimmed and symmetrical output pulses for the AGC circuit 3 and detect circuit 8.

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Adaptive Equalizer for Read Channel

As shown in Fig. 1, an adaptive equalization circuit 1 between preamplifier 2 and AGC circuit 3 of a read channel employs differential sum slimming of both leading and trailing edges. The preamplified readback pulse is differentiated and scaled by a factor A in circuit 4. The output of circuit 4 is then summed with the readback pulse in junction 5 to slim the trailing edge. Similarly, the output of junction 5 is differentiated and scaled by a factor B in circuit 6, the output of which is summed with the input in junction 7 to slim the leading edge. The factors A and B are controlled adaptively in order to produce slimmed and symmetrical output pulses for the AGC circuit 3 and detect circuit 8.

To control the value of A, the amplitudes of prerecorded patterns of data of different frequencies are compared in resolution measuring circuit 9 to produce a control voltage V(c). In the case of MFM recording, patterns of transitions at 1F and 2F density, where F is the cell frequency, would be recorded. The value of B is controlled by both the resolution measurement and the output V(cr) of a pulse asymmetry measuring circuit 10. A combined control voltage V(c)' for determining factor B is generated by multiplier circuitry 11 according to the expression: V'(c) = V(c) (1 - V(cr)). The output of junction 7 is a stream of slimmed symmetrical pulses of substantially constant resolution. The symmetry of the equalized pulses reduces peak shift caused by pulse crowding. Because...