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One Device Memory Cells made using Recessed Gate FET and Four Basic Masking Steps

IP.com Disclosure Number: IPCOM000088549D
Original Publication Date: 1977-Jun-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 21K

Publishing Venue

IBM

Related People

Rideout, VL: AUTHOR

Abstract

Recently, a novel field-effect transistor (FET) structure called a recessed-gate FET has been described [*]. The polysilicon gate electrode of this transistor is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a small polysilicon electrode area that matches the channel region of the FET. Another novel feature of this device is a self-registering electrical connection between the gate electrode and the metallic interconnection line pattern. An oxidation barrier layer of silicon nitride is used to prevent oxidation over the gate. When the nitride layer is removed, the entire gate area is revealed for contacting by a metal line.

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One Device Memory Cells made using Recessed Gate FET and Four Basic Masking Steps

Recently, a novel field-effect transistor (FET) structure called a recessed- gate FET has been described [*]. The polysilicon gate electrode of this transistor is self-aligned on its ends with respect to the conductive source and drain regions, and is also self-aligned on its sides with respect to the nonconductive field oxide isolation regions. This double self-alignment feature results in a small polysilicon electrode area that matches the channel region of the FET. Another novel feature of this device is a self-registering electrical connection between the gate electrode and the metallic interconnection line pattern. An oxidation barrier layer of silicon nitride is used to prevent oxidation over the gate. When the nitride layer is removed, the entire gate area is revealed for contacting by a metal line. This misregistration-tolerant contacting technique and the doubly self- aligned gate electrode structure yield very small FET gate electrodes and a highly planar surface topology. The polysilicon regions can serve only as FET gate electrodes or as MOS capacitor electrodes and cannot be used as inter connection lines. Disclosed here is a one-transistor-per-cell random-access memory made using the recessed-gate FET process.

There are two versions of the recessed-gate FET using four basic lithographic masking steps. In the first version [*] the field channel-stopper doping is formed prior to forming the n+ source and drain regions, while in the second version the source/drain doping precedes the field doping step. Fig. 1 illustrates the masking sequence for the field-first version of the recessed-gate FET process [*]. With the first masking step the device regions are delineated (Fig. 1A). A stack of layers consisting of the gate insulator, the polysilicon gate material, and the nitride oxidation barrier are preserved in the device regions. Thin oxide layers may be used on either side of the nitride layer to aid in its delineation and removal. After etching through the stack of layers, the boron field doping is ion-implanted. Then the thick field oxide is grown by wet thermal oxidation. Oxide does not grow over the device regions which are still protected by the nitride oxidation barrier layer.

The second masking step defines a resist pattern which preserves the nitride layer over the gate electrodes and over the capacitor storage plate electrodes (Fig. 1B). Wherever the two patterns cross each other, a polysilicon electrode will be formed. The nitride and polysilicon are removed by etching in the device regions not covered by the second masking pattern. Then the n+ source and drain regions are formed by diffusion or implantation. Next, a thick insulation oxide is thermally grown over the n+ regions. Now the protective nitride layer can be removed from the polysilicon...