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Avoiding Partial Charges on Droplets in a Binary Ink Jet Printer

IP.com Disclosure Number: IPCOM000088592D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Mix, AL: AUTHOR [+2]

Abstract

The apparatus schematically shown above guarantees that no drops from an ink jet printer will be partially charged. The apparatus also guarantees synchronization when the nozzle performs best at one frequency and the data arrives at another frequency. Waveforms appearing in the apparatus are identified by letters B, D and E. A represents where drop breakoff occurs, and F the drops that are printed. The apparatus is designed for a binary ink jet printer where ink droplets either pass to the printed page or are deflected to a gutter, i.e., drop or no drop, respectively.

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Avoiding Partial Charges on Droplets in a Binary Ink Jet Printer

The apparatus schematically shown above guarantees that no drops from an ink jet printer will be partially charged. The apparatus also guarantees synchronization when the nozzle performs best at one frequency and the data arrives at another frequency. Waveforms appearing in the apparatus are identified by letters B, D and E. A represents where drop breakoff occurs, and F the drops that are printed. The apparatus is designed for a binary ink jet printer where ink droplets either pass to the printed page or are deflected to a gutter,
i.e., drop or no drop, respectively.

In operation, comparator 10 compares an input video signal to a black/white threshold. This yields the data waveform D which is passed to bistable circuit 12. Bistable circuit 12 is gated by clock signal B from oscillator 14. Oscillator 14 provides clock signal B to both the bistable circuit 12 and the drop generator 16. Clock signal B is a square waveform. Positive transitions of clock signal B are used to gate the bistable circuit 12, while negative transitions of the clock signal are used to drive the drop generator 16. Accordingly, the bistable circuit 12 and the drop generator 16 are half of a clock cycle out of phase.

When a positive transition of clock signal B gates bistable circuit 12, the circuit is set to the binary value being received from comparator 10. The binary value of the bistable circuit 12 then controls the charge...