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Matching Circuit Errors to Data Patterns

IP.com Disclosure Number: IPCOM000088599D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Smith, PM: AUTHOR

Abstract

In electrically loadable associative arrays, such as programmable logic arrays, PROMs, and the like, bit positions in a wordline may be stuck, indicating either a zero or a one position. Rather than make the entire wordline inoperative, matching such error patterns to data patterns used to control or operate the associative array bypasses the effect of such defective bits. That is, when a bit is stuck to a zero, a data pattern is inserted in a wordline that has a zero at the defective bit position. Correspondingly, when a bit is stuck to a one, a data pattern having a "1" at the defective bit position is selected. When a plurality of bits are stuck to a predetermined data pattern, a data pattern similar to such stuck bits then can be selected.

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Matching Circuit Errors to Data Patterns

In electrically loadable associative arrays, such as programmable logic arrays, PROMs, and the like, bit positions in a wordline may be stuck, indicating either a zero or a one position. Rather than make the entire wordline inoperative, matching such error patterns to data patterns used to control or operate the associative array bypasses the effect of such defective bits. That is, when a bit is stuck to a zero, a data pattern is inserted in a wordline that has a zero at the defective bit position. Correspondingly, when a bit is stuck to a one, a data pattern having a "1" at the defective bit position is selected. When a plurality of bits are stuck to a predetermined data pattern, a data pattern similar to such stuck bits then can be selected.

Minimization of matching the error pattern to data patterns is achieved by using a very simple sequence of operations. Assume that the wordlines in the associative array are numbered from zero through 49. The array is programmed such that most operational data patterns are inserted at the lower numbered wordlines with the remaining wordlines being NO OP'ed. A NO 0P can be either all zeros or all ones or other data patterns. A NO OP in the array does not have to match the input, bit for bit. For example, the first 35 wordlines in a given array may have data patterns to be associated with inputs, while the last 15 may be all NO OP'ed. 0n the other hand, another array may have 48 lines with data patterns, the last two wordlines being NO OP'ed.

The data patterns to be stored in the various wordlines are loaded in sequence beginning with wordline number zero and extending through wordline number 49. Each wordline is tested as it is loaded for determining whether or not the data pattern loaded is reflected by a readout of the wordline. If not, one or more bits in the loaded wordline are stuck and do not coincide with the loaded data patterns.

At this time the word pattern attempted to be loaded and tested is the highest nu...