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Adaptive Equalization for Digital Recorder Readback Circuits

IP.com Disclosure Number: IPCOM000088601D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 64K

Publishing Venue

IBM

Related People

Luhrs, OR: AUTHOR [+2]

Abstract

Digital signal recorders for high-density recording employing a magnetic record member sensed by a transducer relatively movable thereto divide readback signals through an amplifier, thence to an adaptive or feedback equalizer which supplies equalized signals to a self-clocked detector. At extremely high densities (10,000 flux changes per centimeter), parameter changes in the relationship between the transducer and the record member can shift signals such that equalization should be changed for successful self-clocked detection.

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Adaptive Equalization for Digital Recorder Readback Circuits

Digital signal recorders for high-density recording employing a magnetic record member sensed by a transducer relatively movable thereto divide readback signals through an amplifier, thence to an adaptive or feedback equalizer which supplies equalized signals to a self-clocked detector. At extremely high densities (10,000 flux changes per centimeter), parameter changes in the relationship between the transducer and the record member can shift signals such that equalization should be changed for successful self-clocked detection.

The illustrated apparatus detects and corrects for peak shifting of the readback signal in an adaptive manner. The output signal of the self-clocked detector, and the clock signal are combined in digital circuits to generate equalizer control signals in a digital control for the equalizer circuit. The digital control can be an up/down counter supplying its output signals to the adaptive or feedback equalizer, which can be constructed in accordance with known techniques.

The self-clocked detector includes a comparison circuit (not shown) comparing data times with clock times of a variable frequency oscillator used in the detection process. These comparisons result in phase error signals (PES) which are pulse-width modulated in accordance with the magnitude of the phase error. PES signals are supplied to an integrator which sums the width of the pulses until a threshold V(R) is reached, at which time a threshold circuit supplies an output pulse, squelching the integrator and initiating operation of transfer of equalizing adjustment signals to the digital control, as well as instituting a new measurement cycle. For simplicity purposes, the timing and sequence control circuits are not shown.

The transition counter responds to the data pulses supplied by the self- clocked detector to increment its count. This occurs during the same sample period that the PES signals are being received by the integrator. Accordingly, the number of data transitions counted in the transition counter at output pulse time has a direct relationship to the correction magnitude required for the adaptive or feedback equalizer. For example, if 20 counts are recorded in the transition counter when the integrator level V(R) is reached, a relatively large error signal is indicated; that is, the PES signals are relatively wide indicating a fast integration. On the other hand, if 300 data transitions were counted in the transition counter before the V(R) level was reached by the integrator, a relatively insignificant phase error is indicated, resulting in a rather minor adjustment to the adaptive equalizer.

Assuming that PES indicates the direction of change, then the direction of error can be supplied directly to the digital control from the self-clocked detector. However, if the direction of change is not indicated by PES, a register and compare circuit, receiving t...