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Browse Prior Art Database

Memory Tester Pattern Generator

IP.com Disclosure Number: IPCOM000088610D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 42K

Publishing Venue

IBM

Related People

Geffken, HH: AUTHOR

Abstract

Semiconductor memory devices require extensive testing or exercising in order to determine performance and reliability characteristics. Testers providing required control and timing parameters for newly developed memory devices are not readily available, but may be fabricated from a plurality of discrete functional components as described below.

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Memory Tester Pattern Generator

Semiconductor memory devices require extensive testing or exercising in order to determine performance and reliability characteristics. Testers providing required control and timing parameters for newly developed memory devices are not readily available, but may be fabricated from a plurality of discrete functional components as described below.

This memory tester pattern generator comprises a plurality of flip-flop registers latches and random-access memory modules. A key component of the tester is the Pattern Generator (PG) Memory Array which comprises, for example, 32-1om-access memory modules wired in parallel to provide a 1K word by 32-bit memory. The data stored in the word addresses of the PG Memory Array represent various data and operations to be performed by the tester. A part of the stored word includes a plurality of bits representing the Next PG Address which is fed to a PG Address Counter used to address the Array. When the PG Step Latch output Step and the PG Clock are significant, the PG Address Counter increments by one. When STEP is not significant, the PC Address Counter is set to the Next PG Address. Remaining data bits are applied to the Control Logic Registers and provide read/write (R/W) and data control, Step-Up or Step-Down of Storage Address Counter (SAC) and additional control data which is applied to the PG Function Control and Timing Logic.

The PG Function Control and Timing Logic performs functions such as controlling the application and timing of the Word and Bit address to the Memory Device Under Test and control the conditions under which the PG Step Control enables the PG Step Latch to advance the PG Address Counter to the Next PG Address.

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