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Off Chip Ground Up Receiver

IP.com Disclosure Number: IPCOM000088650D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 70K

Publishing Venue

IBM

Related People

Chen, JZ: AUTHOR [+5]

Abstract

The receiver shown in Fig. 1, is constructed from two internal cells. It is a ground-up receiver which is capable of operating with a +5.0 volt logic swing at its input and approximately a +1.5 ---> 2.0 volt swing at its output. The circuit can be driven by either an open collector driver (w/pull-up resistor) or an active collector driver (push-pull).

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Off Chip Ground Up Receiver

The receiver shown in Fig. 1, is constructed from two internal cells. It is a ground-up receiver which is capable of operating with a +5.0 volt logic swing at its input and approximately a +1.5 ---> 2.0 volt swing at its output. The circuit can be driven by either an open collector driver (w/pull-up resistor) or an active collector driver (push-pull).

This receiver exhibits very high DC noise tolerance in both the up and down level logic states.

Typical average delay is approximately 2.5 nanoseconds at an average power dissipation ~~1.25 milliwatts.

The layout, as implemented in the basic cells, is shown in Fig. 2.

With the input at an up level (logical ces T1 and T2 conduct causing node 1 and all of the Schottky barrier diode (SBD) outputs to assume a low level. The high voltage Schottky DH prevents T1 and T2 from becoming saturated and at the same time allows node 1 to fall low enough to provide adequate down level noise tolerance to the circuits being driven. Utilizing two low voltage SBDs in parallel provides an additional 25 mv down level noise tolerance. Paralleling of devices T1 and T2, available in the two cell implementation, improves the down level noise tolerance by an additional 20 mv. With the input at a low level, the base of T1 and T2 is discharged through the resistor combination R1 and R2, and T1 and T2 turn off quickly (no deep saturation of T1 and T2).

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