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Speed Enhancement of Saturated Transistors

IP.com Disclosure Number: IPCOM000088657D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+2]

Abstract

In integrated digital circuits with saturated transistors, reduced switching speeds have to be tolerated, since the saturation charge storage in the base zone may be substantial.

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Speed Enhancement of Saturated Transistors

In integrated digital circuits with saturated transistors, reduced switching speeds have to be tolerated, since the saturation charge storage in the base zone may be substantial.

By connecting a saturated NPN transistor to a PNP auxiliary transistor, across whose emitter-collector path the excess base current can be discharged, the saturation charge storage can be reduced. By merging a lateral PNP auxiliary transistor and the saturated NPN transistor, a structure is obtained which is ideally suited to integration.

Figs. 1 and 2 show two layouts differing from each other slightly, similar semiconductor zones bearing the same references.

Fig. 1 shows the layout of a vertical NPN transistor with a P- substrate 1, an N- epitaxial layer 2 serving as a collector zone, an N+ subcollector 3, a P base zone 4 embedded in collector zone 2, and an N+ emitter zone 5 arranged in the base zone. Emitter zone 5, base zone 4 and collector zone 2 with an N+ collector terminal region 6 are provided with terminals E, B and C. With this transistor an excess base current is to be discharged. For this purpose base zone 4 is surrounded by a similar P zone 8, forming the collector of the lateral PNP auxiliary transistor. Base zone 5 of the vertical transistor and collector zone 2 simultaneously form the emitter and the base zone, respectively, of the lateral auxiliary transistor.

P zone 8, forming the collector zone of the auxiliary transistor, i...