Browse Prior Art Database

Keyboard Bail Control

IP.com Disclosure Number: IPCOM000088668D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Parrish, MA: AUTHOR

Abstract

A method of electronically controlling the bail codes unique to an electronic output keyboard is described. The bail codes are latched electronically and held until the system samples the codes. After sampling, the latches automatically reset themselves and are ready to accept the next bail input code. This latching of the keyboard bail codes allows more time for the system to perform its necessary tasks before it is forced to sample the keyboard so as not to lose any inputs. Without this latching, the required keyboard sampling rate is much faster.

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Keyboard Bail Control

A method of electronically controlling the bail codes unique to an electronic output keyboard is described. The bail codes are latched electronically and held until the system samples the codes. After sampling, the latches automatically reset themselves and are ready to accept the next bail input code. This latching of the keyboard bail codes allows more time for the system to perform its necessary tasks before it is forced to sample the keyboard so as not to lose any inputs. Without this latching, the required keyboard sampling rate is much faster.

If the system is ready to accept keyboard input, signal S* will be high (an uplevel, logical "1") and GATE will be low. Eight switches, requiring latches, originate in the keyboard. Six of these are OR'ed together through the Nolr circuit. Upon closure of any switch, the output of Nolr will go to a low level. For simplicity, this illustration will use Bail 1 only. Upon closure of the Bail 1 switch, the latch signal BL1 will go high, ultimately forcing signal S high. After a period of time, S* will go low. This delay assures that all switches have stopped bouncing and are ready for system sampling. With S* low, the latch is activated, thereby retaining the value of BL1 for as long as necessary. The switches are out of the system now. Upon reception of the SAMPLE signal, the latch outputs are gated out to the system for use. After the sample is completed, the GATE signal will go high, forcing S* hi...