Browse Prior Art Database

Pin Sharing in a PLA Code

IP.com Disclosure Number: IPCOM000088678D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Wu, WW: AUTHOR

Abstract

Module pins 10 to 16 can be shared by enabling and disabling the AND gates 20 thru 34 and inverter 36 with a control signal on a single module pin 38.

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Pin Sharing in a PLA Code

Module pins 10 to 16 can be shared by enabling and disabling the AND gates 20 thru 34 and inverter 36 with a control signal on a single module pin 38.

When the control signal is up, a completely different set of circuits is connected to the pins 10 to 16 by AND gates 26 thru 30 and 34 then are connected to pins 10 to 16 by AND gates 22, 24 and 34 when the control signal is down. Thus the pins can be used in performing two functions. For instance, they can be fed test signals while the module is being tested, and then used for other purposes when the module is operational.

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