Browse Prior Art Database

Buffer Block Prefetching Method

IP.com Disclosure Number: IPCOM000088692D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Gindele, JD: AUTHOR

Abstract

The prefetching method is provided for a processor having a high speed buffer (i.e., cache), which operates as follows:

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Buffer Block Prefetching Method

The prefetching method is provided for a processor having a high speed buffer (i.e., cache), which operates as follows:

A block of data may be transferred from processor main storage to the cache by a "fetch" or a "prefetch". A "fetch" is defined as an access of a cache block from main storage caused by a CPU reference that misses in the cache (as implemented in current systems). A "prefetch" is the obtaining of another cache block from main storage in advance of any CPU reference to it. A prefetch is initiated by the first CPU reference to a block after it is put into the cache. The prefetch transfers into the cache the next sequential block after the block having the cache hit. The sequential relationship of blocks refers to their main storage addressed locations and not to their cache locations.

The prefetch is accomplished with the aid of a special bit (prefetch bit) associated with each block location in the cache. A '0' setting for a prefetch bit means that its block has not been referenced, and a '1' setting indicates that it has been referenced. When a block is transferred from main storage to the cache, the prefetch bit is set to '0'. When a cache block is accessed by the CPU for the first time, the prefetch bit is then set to '1'. When the prefetch bit is changed from '0' to '1', a prefetch cycle is triggered which causes a search in the cache for the next sequential block. If it is not found in the cache, the block is prefetched from main storage.

In effect, a cache mis...