Browse Prior Art Database

Sequentially Addressed Storage

IP.com Disclosure Number: IPCOM000088708D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 56K

Publishing Venue

IBM

Related People

Hannaford, CW: AUTHOR

Abstract

From an implementation standpoint, it is frequently undesirable to embody a sequentially addressed storage unit as a shift register. Instead, it is built up of a random-access array of storage cells 10, with an on-chip address generator 20 which connects sequential storage locations to external data lines 11 and 12 when the array is enabled by line 21. Addresses are sequenced by pulses on clock line 22.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 66% of the total text.

Page 1 of 2

Sequentially Addressed Storage

From an implementation standpoint, it is frequently undesirable to embody a sequentially addressed storage unit as a shift register. Instead, it is built up of a random-access array of storage cells 10, with an on-chip address generator 20 which connects sequential storage locations to external data lines 11 and 12 when the array is enabled by line 21. Addresses are sequenced by pulses on clock line 22.

Decoder 20 could assume one of several different forms. A binary counter is, itself, quite compact, but requires a large, complex decoder to provide a unique address signal for every different cell in array 10. A "walking bit" shift register, containing all zeros except for a single stage, requires no decoder, but does require a separate shift-register stage (physically as large as a counter stage) for every address in array 10. The decoder shown above requires only half as many stages as a walking-bit register, yet has a decoder which is much simpler than that for a binary counter. Flip-flops 23 are connected together as a conventional Johnson counter, also known as a twisted-ring or Moebius counter. AND gates 24 then decode the states of adjacent flip-flop stages to provide the required unique address signals 25. The progression of states is then as shown below, where the underlines represent the flip-flop outputs which are decoded to produce the corresponding address signals 25. Flip-Flops 23 Signals 25

0000---0 1000---0000

1000--...