Browse Prior Art Database

Frequency Divide by Three With Symmetry

IP.com Disclosure Number: IPCOM000088711D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Pellinger, RD: AUTHOR

Abstract

Trigger 1 and trigger 2 are a pair of D-type flip-flops connected as a two-bit shift register, with NOR 1 used to recirculate the bit in the shift register automatically while providing the timing of a three-bit shift register. NOR 3 and NOR 4 are connected as a set-reset latch, while NOR 2 develops the reset for the latch. This circuit functions to provide at the output (F/3 OUT) a symmetrical signal having one-third the frequency of the input signal (F IN).

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Frequency Divide by Three With Symmetry

Trigger 1 and trigger 2 are a pair of D-type flip-flops connected as a two-bit shift register, with NOR 1 used to recirculate the bit in the shift register automatically while providing the timing of a three-bit shift register. NOR 3 and NOR 4 are connected as a set-reset latch, while NOR 2 develops the reset for the latch. This circuit functions to provide at the output (F/3 OUT) a symmetrical signal having one-third the frequency of the input signal (F IN).

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