Browse Prior Art Database

High Speed Data Transfer Circuitry

IP.com Disclosure Number: IPCOM000088712D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 62K

Publishing Venue

IBM

Related People

Dumstorff, EF: AUTHOR [+2]

Abstract

In a particular I/O controller (IOC), it normally takes two sequential instructions to transfer data between the I/O device adapter and the IOC. For example, when data is transferred from the IOC to the I/O device adapter a load indirect instruction (LN) causes data to be moved from data storage (DS) to a register (REG space). An I/O write (IOW) instruction then transfers the data from REG space to the I/O adapter. Similarly, when data is to be transferred from the I/O device adapter to the IOC, an I/O read (IOR) instruction transfers the data from the I/O device adapter to REG space in the IOC. A store instruction (STN) moves the data from REG space into DS. The high-speed data transfer circuitry accomplishes the data transfer with a single instruction.

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High Speed Data Transfer Circuitry

In a particular I/O controller (IOC), it normally takes two sequential instructions to transfer data between the I/O device adapter and the IOC. For example, when data is transferred from the IOC to the I/O device adapter a load indirect instruction (LN) causes data to be moved from data storage (DS) to a register (REG space). An I/O write (IOW) instruction then transfers the data from REG space to the I/O adapter. Similarly, when data is to be transferred from the I/O device adapter to the IOC, an I/O read (IOR) instruction transfers the data from the I/O device adapter to REG space in the IOC. A store instruction (STN) moves the data from REG space into DS. The high-speed data transfer circuitry accomplishes the data transfer with a single instruction. The high-speed data transfer circuitry is in the I/O device adapter, and is conditioned by a control signal from the IOC. The high-speed data transfer circuitry essentially decodes the LN and STN instructions to force IOW and IOR signals, respectively. Hence, data transfer can take place with single instructions because these instructions are also being decoded in the IOC for their normal function.

Only a portion of the IOC 10 and I/O device adapter 50 are shown in the drawing. The instructions executed by IOC 10 are fetched from control storage (CS) 51 by a conventional addressing mechanism (not shown). The logic in IOC 10 for decoding and executing the instruction is also not shown. The high-speed control line 1l is activated under program control, and when active, it conditions decode logic blocks 53-56, inclusive, in I/O device adapter 50.

Logic block 53 functions to decode an LN instruction in device adapter 50. The LN...