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Sequence Controller Using Programmable Logic Array

IP.com Disclosure Number: IPCOM000088713D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 41K

Publishing Venue

IBM

Related People

Hicks, DR: AUTHOR

Abstract

A programmable logic array (PLA) may be used as a sequence controller by providing inputs representing external status or condition signals, providing control outputs to the system to be controlled, and feeding back some of the outputs to the inputs, to represent the current state of the controller. Although the output width of most PLAs is limited, the effective number of outputs may be increased by using them to address a read-only storage (ROS), which may then be made as wide as necessary. But most PLAs are also quite limited in the number of product terms which are implemented, so that several relatively expensive PLA modules must frequently be connected in parallel.

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Sequence Controller Using Programmable Logic Array

A programmable logic array (PLA) may be used as a sequence controller by providing inputs representing external status or condition signals, providing control outputs to the system to be controlled, and feeding back some of the outputs to the inputs, to represent the current state of the controller. Although the output width of most PLAs is limited, the effective number of outputs may be increased by using them to address a read-only storage (ROS), which may then be made as wide as necessary. But most PLAs are also quite limited in the number of product terms which are implemented, so that several relatively expensive PLA modules must frequently be connected in parallel.

Circuit 10 (Fig. 1) increases the effective number of product terms in PLA 11. Frequently, a large number of the "next-state" outputs 12 depend only upon the "current-state" or feedback signals 13 from ROS 14, so that status inputs 15 would be coded as "don't-care" in selecting the next product term. One line 16 of feedback signals 13, representing one bit of ROS 14, controls a counter 17 placed between PLA 11 and ROS 14. This bit is coded "low" for states whose successors require status inputs 15; line 16 then commands counter 17 to load PLA outputs 12 and to transfer them directly to ROS address lines 18. But, when inputs 15 are not needed, a "high" level on line 16 allows clock signal 19 to increment counter 17; lines 18 now address the next h...