Browse Prior Art Database

Independent Use in a Logic Circuit of Level Sensitive Latches in a Shift Register Stage

IP.com Disclosure Number: IPCOM000088715D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 37K

Publishing Venue

IBM

Related People

Cochran, WH: AUTHOR [+2]

Abstract

The difficulties of performing functional tests on large-scale integrated circuits has led to a diagnostic concept known as level-sensitive scan design (LSSD), as described in U. S. Patent 3,783,254. Very briefly, a logic design using LSSD is divided into purely combinatorial circuits and storage elements. All storage elements have two level-sensitive latches 10, 20 (Fig. 1), permitting their interconnection into a shift-register chain for the entry of diagnostic, or "scan-in" data I by a shift clock A. The normal-mode inputs are system data D and system clock C. The normal output is L1 from latch 10. Although L2 is normally connected to the I input of another stage, this signal may also be coupled within the logic circuit subject to certain restrictions.

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Independent Use in a Logic Circuit of Level Sensitive Latches in a Shift Register Stage

The difficulties of performing functional tests on large-scale integrated circuits has led to a diagnostic concept known as level-sensitive scan design (LSSD), as described in U. S. Patent 3,783,254. Very briefly, a logic design using LSSD is divided into purely combinatorial circuits and storage elements. All storage elements have two level-sensitive latches 10, 20 (Fig. 1), permitting their interconnection into a shift-register chain for the entry of diagnostic, or "scan-in" data I by a shift clock A. The normal-mode inputs are system data D and system clock C. The normal output is L1 from latch 10. Although L2 is normally connected to the I input of another stage, this signal may also be coupled within the logic circuit subject to certain restrictions.

One of these restrictions is that L1 and L2 cannot be coupled to the same combinatorial logic circuit. However, it is often desirable to do just that. In decoders and arithmetic/logic-unit registers, for example, half of the latches may be unavailable for use because of this restriction, thus necessitating twice the number of latches otherwise required. The restriction arises because L1 is normally coupled directly to the input of slave latch 20 along with shift clock B, and, hence, cannot be freed from L1 for test purposes.

The circuit of Fig. 1 overcomes this limitation by placing transfer device 30 between output L1 and the input of latch 20.

During normal operation,...