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Tristate Programmable Driver Circuit

IP.com Disclosure Number: IPCOM000088725D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 53K

Publishing Venue

IBM

Related People

Marez, GJ: AUTHOR

Abstract

This tristate driver circuit has low leakage (a few microamperes) in the tristate, wide dynamic range, high slew rate, a minimum of overshoot and undershoot, and is capable of sourcing or sinking 40 ma current on demand. The output stage is protected against shorts to supply voltages or ground. The data input is T/2/L, therefore a standard T/2/L inverter precedes a level shifting subcircuit comprising a transistor 22, resistors 24 and 26 and a transistor 28, which lowers the output impedance. A differential amplifying circuit, comprising a pair of transistors 30 and 32, is biased so that a current source transistor 34 has adequate compliance voltage applied thereto.

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Tristate Programmable Driver Circuit

This tristate driver circuit has low leakage (a few microamperes) in the tristate, wide dynamic range, high slew rate, a minimum of overshoot and undershoot, and is capable of sourcing or sinking 40 ma current on demand. The output stage is protected against shorts to supply voltages or ground. The data input is T/2/L, therefore a standard T/2/L inverter precedes a level shifting subcircuit comprising a transistor 22, resistors 24 and 26 and a transistor 28, which lowers the output impedance. A differential amplifying circuit, comprising a pair of transistors 30 and 32, is biased so that a current source transistor 34 has adequate compliance voltage applied thereto.

The predrive and output circuitry are designed to operate in a linear mode so that the output stage follows a wide range of reference levels with minimum error. The circuit somewhat resembles a simple unity-gain voltage follower. Sourcing current transistors 36, 30, a diode 38, and a transistor 40 comprise the predrive circuitry for an output stage transistor 42. The voltage is sampled by the transistor 40 and the output is forced to seek an up reference level applied through a diode 44. Transistors 32, 46 and 52 and diodes 48 and 50 are off during this interval also; a sink transistor 54 is switched off to conserve power. The base-to-emitter voltages of the diodes 44, 58, 38 and 56, and the transistors 36, 40 tend to cancel, and any mismatches due to different current levels detract little from the final output. During the sinking interval the transistor 32 takes all of the current away from the transistor 30, and diode 38 is back biased, whereby the transistor 46 and diode 48 share the current. The transistor 52 buffers the transistor 54 from the transistor 32 and also provides the correct level to turn the transistor 54 on. The collector of the transistor 52 draws about 1.0 ma during this period, preconditioning a critical node at the emitter of the transistor 40 which enhances the fall time. The output is the same polarity as the data input; that is, when the data level is high, the driver sources current, and when the data level is low, the driver sinks current. The external source and sink curren...