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Data Demodulator Circuit Arrangement

IP.com Disclosure Number: IPCOM000088726D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Fiehmann, DE: AUTHOR [+3]

Abstract

This circuit arrangement is particularly useful in frequency shift keying radio data transmission systems and is applicable to any system in which tracking of the mean amplitude of a bistatic signal is desired.

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Data Demodulator Circuit Arrangement

This circuit arrangement is particularly useful in frequency shift keying radio data transmission systems and is applicable to any system in which tracking of the mean amplitude of a bistatic signal is desired.

An incoming data signal is applied at input terminals 10,12. The signal is not in the desired square-wave form because of bandwidth restrictions, frequency response drift due to temperature variations, bit shift effects in magnetic transducer reproduction and the like. The input signal is applied essentially in parallel to three comparators 14,16,18.

The comparator 16, a rectifier 26 and a capacitor 28 form a positive peak detector circuit. The comparator 14, rectifier 30, and capacitor 32 form a negative peak detector circuit. Two resistors 34,36 form a center-tapped voltage divider that provides a centered mean reference level to the comparator 18. The latter delivers a bistatic square wave signal at output terminals 40, 42.

Reset pulses applied at terminals 44,46 cause transistors 48,50 to conduct and discharge the capacitors 28 and 32. Diodes 52 and 54 alternately are Zener diodes, and alternately are omitted.

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