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High Performance Differential Amplifier Input Stage

IP.com Disclosure Number: IPCOM000088752D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 40K

Publishing Venue

IBM

Related People

Jaeger, RC: AUTHOR

Abstract

It has previously been demonstrated that the differential amplifier input stage illustrated in Fig. 1 has a significant common-mode rejection ratio (CMRR) sensitivity to load element imbalance which other stages, such as the differential pair and differential cascode stages, do not exhibit. High CMRR sensitivity to load element imbalance is an indication that the bias current of the amplifier is shifting as the common-mode input voltage changes. Computer analysis has also shown that the bias current variations in the input stage of Fig. 1 are caused by the finite output resistance of the PNP transistors which operate in the "current mirror" configuration.

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High Performance Differential Amplifier Input Stage

It has previously been demonstrated that the differential amplifier input stage illustrated in Fig. 1 has a significant common-mode rejection ratio (CMRR) sensitivity to load element imbalance which other stages, such as the differential pair and differential cascode stages, do not exhibit. High CMRR sensitivity to load element imbalance is an indication that the bias current of the amplifier is shifting as the common-mode input voltage changes. Computer analysis has also shown that the bias current variations in the input stage of Fig. 1 are caused by the finite output resistance of the PNP transistors which operate in the "current mirror" configuration.

The improved amplifier stage of Fig. 2 significantly improves the CMRR of the differential amplifier by replacing the PNP current mirrors with "Wilson" current sources. Along with improved CMRR, the available voltage gain of the stage is substantially improved because the overall stage exhibits a much higher output resistance. The active load configuration of Fig. 2 replaces that of Fig. 1 to utilize this available gain. An order of magnitude improvement is obtained in CMRR. CMRR sensitivity to load element mismatch is eliminated. Further, offset voltage sensitivity to early voltage mismatch in devices PNP3 and PNP4 is also eliminated.

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