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Browse Prior Art Database

Generating Prime Faults of Combinational Circuits for Single Stuck Faults

IP.com Disclosure Number: IPCOM000088757D
Original Publication Date: 1977-Jul-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 118K

Publishing Venue

IBM

Related People

Cha, CW: AUTHOR

Abstract

The flow chart below illustrates a procedure for use in automated circuit design methods for generating a set of prime faults that can be used to generate a single stuck fault detection test set such that any detectable single stuck fault in a combinational circuit will be detected by the test set. (Image Omitted)

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Generating Prime Faults of Combinational Circuits for Single Stuck Faults

The flow chart below illustrates a procedure for use in automated circuit design methods for generating a set of prime faults that can be used to generate a single stuck fault detection test set such that any detectable single stuck fault in a combinational circuit will be detected by the test set.

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