Browse Prior Art Database

Cylinder Fault Processing

IP.com Disclosure Number: IPCOM000088803D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 29K

Publishing Venue

IBM

Related People

Boon, CE: AUTHOR [+7]

Abstract

A multilevel store, having a partitioned upper level and a common lower level, has data accessed by a virtual addressing technique called virtual volumes, cylinders and tracks. Data signals are staged from the common lower level to the partitioned upper level on a cylinder, or a plurality of cylinders, basis. A mass storage control (MSC) controls the staging and destaging of data. Transfers between the partitioned upper level store and a plurality of hosts is achieved through a plurality of DIRSAs which act as staging adaptors and connect to channels of the host. The term "DIRSA" means director and staging adaptor.

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Cylinder Fault Processing

A multilevel store, having a partitioned upper level and a common lower level, has data accessed by a virtual addressing technique called virtual volumes, cylinders and tracks. Data signals are staged from the common lower level to the partitioned upper level on a cylinder, or a plurality of cylinders, basis. A mass storage control (MSC) controls the staging and destaging of data. Transfers between the partitioned upper level store and a plurality of hosts is achieved through a plurality of DIRSAs which act as staging adaptors and connect to channels of the host. The term "DIRSA" means director and staging adaptor.

Final Status for a faulted cylinder seek is Channel End (CE), Device End (DE) and Status Modifier (additional information) enabling channel/host programs to be instructed for handling the situation. Upon such a fault, the channel/host program terminates, freeing a Virtual Unit (VU) in the multilevel store as well as a unit control block (UCB) in the host. This action makes a virtual volume (VV) available during resolution of the cylinder fault. Otherwise, the channel host program executes normally.

It is desired that when a host attempts to access data in the partitioned upper level that the appropriate DIRSA signifies to MSC, via a cylinder fault message, that data signals contained in the common lower level should be staged to the partitioned upper level.

Upon receiving the cylinder fault message from DIRSA, MSC checks to see if the requested cylinder has already been scheduled to be staged or destaged. If scheduling has not occurred, then MSC allocates space in the upper level store and schedules a staging operation. On the other hand, in some instances, stage scheduling has already occurred. In this case, the cylinder fault message is merged with the previous stage scheduling. At this time DIRSA supplies completion status to the requesting host, i.e., ATTENTION.

At the time, the set of cylinders (page) is validated, i.e., the staging is completed. It can occur that the staging has been scheduled but the cylinder fault message cannot be successfully merged in the usual manner with the previous...