Browse Prior Art Database

Load Balancing Control for Multiprocessors

IP.com Disclosure Number: IPCOM000088808D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 52K

Publishing Venue

IBM

Related People

Baker, JF: AUTHOR [+2]

Abstract

With a loosely-coupled multiprocessor-controlled storage or memory system, maximum throughput affected by the proper work-load balance between processors. In order to assure the proper work-load balance, either a master processor may be designated as the controller or multiple processors must be kept informed of all work loads and share the controller's role. The volume of communications required between processors to keep the controllers adequately informed can be costly depending on the controlling procedures. The described mechanism keeps all processors adequately informed of the necessary load balance parameters with minimum communications required between processors. The described communication frequency is adjustable based on system needs.

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Load Balancing Control for Multiprocessors

With a loosely-coupled multiprocessor-controlled storage or memory system, maximum throughput affected by the proper work-load balance between processors. In order to assure the proper work-load balance, either a master processor may be designated as the controller or multiple processors must be kept informed of all work loads and share the controller's role. The volume of communications required between processors to keep the controllers adequately informed can be costly depending on the controlling procedures. The described mechanism keeps all processors adequately informed of the necessary load balance parameters with minimum communications required between processors. The described communication frequency is adjustable based on system needs.

In the loosely-coupled system being addressed, each processor has an equal amount of system control responsibility (i.e., there is no master-slave relationship). This system consists of two or more processors with an interprocessor communication facility. Load balance information is maintained in each processor's dedicated general memory. Load balance parameters indicate the utilization of each processor (e.g., work queue depth). Each processor executes a timed process and a recorder function, and provides command HALT and RESUME functions. Each processor maintains a Load Balance Table. The use of these functions and facilities for load balancing is described below.

During system initialization, a timed process is scheduled in one of the processors. The timed process, when activated, updates the parameters that measure the utilization...