Browse Prior Art Database

True and Complement High Level Signal Circuit

IP.com Disclosure Number: IPCOM000088818D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Parikh, GH: AUTHOR

Abstract

The circuit, shown in Fig. 1, provides true and complement high level signals from a true low level signal. This circuit is particularly useful for random-access memories wherein a plurality of bits, e. g., eight, may be stored at the same time.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 53% of the total text.

Page 1 of 3

True and Complement High Level Signal Circuit

The circuit, shown in Fig. 1, provides true and complement high level signals from a true low level signal. This circuit is particularly useful for random- access memories wherein a plurality of bits, e. g., eight, may be stored at the same time.

In the operation of this circuit formed in a semiconductor chip, during standby when the chip select pulse CS and the delayed chip select or word pulse VW are at their low value, the restore pulse R, indicated in Fig. 2, turns on transistors T1 and T2, which applies a voltage to nodes N1 and N2 having a value equal to VH minus one threshold, VH-VT, and turn on transistors T13 and T14 to apply a similar voltage to nodes NS and N6. Furthermore, during the restore pulse R, transistors T7 and T8 discharge nodes N3 and N4 to ground potential. Either during or after restore pulse R, data gate pulse DG1 is applied to the gate electrode of transistor T15 to store data from the Data In terminal to the gate electrode of transistor T5. The Data In signal passing through T15 is valid while the DG1 pulse is on. Data is stored sequentially on, e.g., seven additional gate electrodes of transistors corresponding to transistor T5, by applying pulses DG2 through DG8, as indicated in Fig. 2, on gate electrodes of other transistors corresponding to transistor T15.

After restore pulse R falls and chip select pulse CS rises, transistors T3 and 14 are turned on. If data stored on the gate electrode of T5 is high, then nodes N3 and N1 are discharged to ground potential through T5. Transistor T5 is designed so that during the discharge of nodes N1 and N3, the voltage on node N3 does not rise to a threshold voltage in order to assure that T6 remains off. Transistor T6 is designed with a longer channel length than T5 so that it has a larger threshold voltage than T5, to provide further assurance that T6 does not turn on when no...