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Optimized Thickness of Silicon Nitride Silicon Dioxide Dielectric for Semiconductor Processing

IP.com Disclosure Number: IPCOM000088852D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 88K

Publishing Venue

IBM

Related People

Bong, A: AUTHOR [+3]

Abstract

It has been shown [*] that a considerable pipe reduction for NPN transistors is achieved by replacing a 1600 Angstroms-thick silicon nitride layer in the pre-emitter passivation layer structure consisting of 800 Angstroms of thermal silicon dioxide 1600 Angstroms of silicon nitride with a 500 Angstroms-thick silicon nitride layer. The improvement is apparently due to a stress reduction for the passivation layer structure, particularly at the edges of the emitter defined by the composite nitride/oxide layer.

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Optimized Thickness of Silicon Nitride Silicon Dioxide Dielectric for Semiconductor Processing

It has been shown [*] that a considerable pipe reduction for NPN transistors is achieved by replacing a 1600 Angstroms-thick silicon nitride layer in the pre- emitter passivation layer structure consisting of 800 Angstroms of thermal silicon dioxide 1600 Angstroms of silicon nitride with a 500 Angstroms-thick silicon nitride layer. The improvement is apparently due to a stress reduction for the passivation layer structure, particularly at the edges of the emitter defined by the composite nitride/oxide layer.

We have found that a similar improvement in pipes may be achieved by using the same thickness of silicon nitride when forming dielectric isolation regions which isolate the base and emitter of the transistor from other regions. A certain quantity of the pipes apparently begin during the recessed oxide process; they subsequently propagate into the emitter area as a consequence of subsequent heat cycles. Thus, to eliminate a majority of the pipes, the dielectric stress of the composite silicon nitride/silicon dioxide layer must be reduced both at the recessed oxide isolation step as well as at the emitter diffusion step.

The step of forming the windows 53 and 53', which define the recessed oxide isolation regions, is shown in Fig. 1. The device comprises a silicon substrate 42 in which N+ subcollector region 47 and P+ isolation region 46 are formed in conventional fas...