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Polarity Hold Latch in a Shift Register Latch to Decrease the Minimum Pulse Width for Test Cycle Time

IP.com Disclosure Number: IPCOM000088861D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Barish, AE: AUTHOR [+3]

Abstract

A general reference is made to a Level Sensitive Logic System of the type disclosed in U. S. Patent 3,783,254 and to the methods of testing the same disclosed in U. S. Patents 3,761,695 and 3,784,907. The latch L2 of Fig. 1 is a polarity hold latch employed in a shift register latch (not shown). The latch holds data opposite in polarity to that of its input. It has only a one phase output (+L2) of data and is clocked by only one phase of the clock (+B).

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Polarity Hold Latch in a Shift Register Latch to Decrease the Minimum Pulse Width for Test Cycle Time

A general reference is made to a Level Sensitive Logic System of the type disclosed in U. S. Patent 3,783,254 and to the methods of testing the same disclosed in U. S. Patents 3,761,695 and 3,784,907. The latch L2 of Fig. 1 is a polarity hold latch employed in a shift register latch (not shown). The latch holds data opposite in polarity to that of its input. It has only a one phase output (+L2) of data and is clocked by only one phase of the clock (+B).

Latching a "0" output (input of "1") is a comparatively fast operation because the output transistor TX has a relatively high base drive. This high base drive is essential to charge the capacitance at the base of output transistor TX and to turn on TX. Due to this higher base drive, the turn-off of the output transistor TX takes more time. This means that putting a "1" into the output of the latch L2 is slowed down. In addition, the output load capacitance further slows the latch action.

Hence, writing a "1" (input of "0") into the latch becomes relatively slow. This increases the minimum pulse width (mpw) requirement of the latch. This larger mpw impacts the machine timing directly and the impact on the cycle time is greater because the clock has to be "ON" longer in time than "OFF" (Fig. 2). This is a restriction on machine timing. Hence, the mpw has to be minimized.

A solution is to add two more collector resis...