Browse Prior Art Database

200 MHz Timing System

IP.com Disclosure Number: IPCOM000088862D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 54K

Publishing Venue

IBM

Related People

Chang, YE: AUTHOR [+2]

Abstract

Fig. 1 depicts only one channel of programmable delay in a system providing a time reference pulse T REF. The cycle time of the system is programmable from 5 nanoseconds to 2.56 microseconds. The timing delay is continuously programmable from zero to cycle time.

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200 MHz Timing System

Fig. 1 depicts only one channel of programmable delay in a system providing a time reference pulse T REF. The cycle time of the system is programmable from 5 nanoseconds to 2.56 microseconds. The timing delay is continuously programmable from zero to cycle time.

Reference is made to the high resolution digitally programmable delay for multichannel operation disclosed in U. S. Patent 3,913,021.

Repetition rate control bits are XOR'ed with the CNTR bits (XOR(I)). The output of XOR(I) is ANDed with Divide 2 to reset control, and provides a pulse which is ANDed with the period synthesizer output to generate one of the T REF's (B). Coarse delay control bits are XOR'ed with the CNTR bits (XOR(II)). The output of XOR(II) is ANDed with the period synthesizer and used to gate fine delay I to "E".

Fig. 2 shows a typical fine delay circuit. The output frequency always follows the input. The phase shift or, in other words, the timing of the output is controlled by the control voltage.

The Fine Delay I (Fig. 1) uses a VCO with a tuning range of 50 to 100 MHz (20 to 10 ns cycle time). The Fine Delay II uses a VCO with a tuning range of 100 to 200 MHz (10 to 5 ns cycle time). The period synthesizer is programmable from 5 to 10 ns in 0.1 steps. For cycle time greater than or equal to 10 ns, the multiplexer (MPX) selects "B" for T REF and "E" for programmable delay. For cycle time less than 10 ns, the MPX's select "A" for T REF and "F" for programmable delay...