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High Speed Array Assisted Binary Decimal Divider

IP.com Disclosure Number: IPCOM000088867D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 85K

Publishing Venue

IBM

Related People

Singh, S: AUTHOR

Abstract

High speed division is accomplished using a high speed multiply unit. The dividend (Np) and the divisor (Dp) are premultiplied by the same approximate inverse (R) of the divisor. The new divisor (D) becomes almost equal to unity and the new dividend (N) becomes almost equal to the required quotient. The m leading high order digits of the new dividend (N) are correct quotient digits where the inverse (R) was obtained using the m + 1 leading high order digits of the original divisor (Dp). A successive subtraction, nonrestoring division is performed using the new divisor (D) and the new dividend (N), each iteration yielding m more digits of the desired quotient.

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High Speed Array Assisted Binary Decimal Divider

High speed division is accomplished using a high speed multiply unit. The dividend (Np) and the divisor (Dp) are premultiplied by the same approximate inverse (R) of the divisor. The new divisor (D) becomes almost equal to unity and the new dividend (N) becomes almost equal to the required quotient. The m leading high order digits of the new dividend (N) are correct quotient digits where the inverse (R) was obtained using the m + 1 leading high order digits of the original divisor (Dp). A successive subtraction, nonrestoring division is performed using the new divisor (D) and the new dividend (N), each iteration yielding m more digits of the desired quotient.

M quotient digits per divide iteration can also be obtained by using only m higher order digits of the original divisor (Dp) to obtain the approximate inverse
(R). However, the quotient formed must be corrected by a correction network. The complexity of the required quotient correction network varies inversely with the bit size of the ROM which stores the approximate inverse (R) of the divisor (Dp).

The successive, nonrestoring division operations of the structure of Fig. 1 will be explained with the aid of the decimal numeric example of Fig. 2. The data flow shown in the example is arranged to provide 8 bits of quotient per divide iteration. The ROM (not shown) which stores the approximate inverse (R) of the divisor (Dp) applies the appropriate R signal via line 1 to working register E3. RA1 and RA2 are two register arrays which store the multiples of the new divisor (D) and shifted multiples of D, respectively. Working registers E1, E2 and E4 provide buffering to facilitate reading and writing with respect to arrays RA1 and RA2.

The properly shifted multiples of the divisor are read into E1 and E2. E4 contains the remainder during each divide iteration. As previously mentioned, E3 stores the divisor D. The higher order 2 digits of the partial dividend (left 8 shifted remainder) in each divide iteration are fed to the multiple decode...