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Reducing the Carrier Storage in Collector Base Junctions

IP.com Disclosure Number: IPCOM000088876D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 57K

Publishing Venue

IBM

Related People

Berger, HH: AUTHOR [+3]

Abstract

In conventional transistor structures high carrier storage at the collector base junction occurs when operating the latter in an inverse direction (e.g., in the case of saturated transistors or in MTL (merged transistor logic) and I/2/L (integrated injection logic)). This leads to an unnecessary decrease in the switching speed.

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Reducing the Carrier Storage in Collector Base Junctions

In conventional transistor structures high carrier storage at the collector base junction occurs when operating the latter in an inverse direction (e.g., in the case of saturated transistors or in MTL (merged transistor logic) and I/2/L (integrated injection logic)). This leads to an unnecessary decrease in the switching speed.

Substantial carrier storage occurs when the doping level from the PN junction towards both sides is initially low and then rises steeply. The low doping causes a great number of minority carriers to be sent from both sides across the PN junction. These carriers accumulate before the highly doped zone. As the switching time constant can be represented by the quotient of charge and current, it is relatively high in the given circumstances.

Fig. 1 shows the standard profile of a base diffusion into the epitaxy (above a subcollector). From this it would seem useful to place the point of intersection xj of the two doping curves at higher values N(A), N(D) by selecting a smaller epi thickness d for a constant base profile. However, in such a case intrinsic base width Wb would also become a function of the inevitably varying epi thickness, as shown in Fig. 2. Thus, in the interest of a satisfactory control of the base width, the epitaxial layer must be made thicker by its own thickness tolerance, in order to ensure that the base and collector profile intersect in the doping plateau.

In inverse transistors (e.g., MTL/I(2)L), the typical ratio of the intrinsic base surface to the overall base surface is 1 : 3, i.e., for 2/3 of the base diffusion the above-mentioned control problems can be overcome. The carrier storage of this (external) base surface can be considerably reduced if, for example, following the epitaxy a mask is applied which is complementary with regard to the emitter zones, and if the silicon outside the emitter zones provided later is etched off by making ample the thickness tolerance of the epitaxy. At the end of the process, an MTL transistor, for example, has the cross-section shown schematically in Fig. 3. In this cas...