Browse Prior Art Database

Input Bus Switching for PLA

IP.com Disclosure Number: IPCOM000088882D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Long, GB: AUTHOR

Abstract

In many applications of Programmed Logic Arrays (PLA) a similar application, such as parity checking, must be performed on more than one input bus. Input bus multiplexing gates 11, controlled by an output polarity hold latch 13, may be used to avoid the need for duplicating the application personality in the array. Latch 13 may, in turn, be controlled by inputs 15 and a product term in the AND array.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Input Bus Switching for PLA

In many applications of Programmed Logic Arrays (PLA) a similar application, such as parity checking, must be performed on more than one input bus. Input bus multiplexing gates 11, controlled by an output polarity hold latch 13, may be used to avoid the need for duplicating the application personality in the array. Latch 13 may, in turn, be controlled by inputs 15 and a product term in the AND array.

1

Page 2 of 2

2

[This page contains 2 pictures or other non-text objects]