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High Density ROS Partitioning

IP.com Disclosure Number: IPCOM000088899D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Gladstein, LA: AUTHOR

Abstract

A read-only storage (ROS) chip architecture is disclosed to minimize the capacitive loading at the output.

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High Density ROS Partitioning

A read-only storage (ROS) chip architecture is disclosed to minimize the capacitive loading at the output.

In a read-only storage chip having a total bit count of N = 2(m+n), the bits may be organized into a number 2/n/ cells of 2/m/ bits each, as shown in the figure. To address the N bits, m+n address bits are required on the chip. In accordance with the cellular architecture disclosed, m of the address lines representing the low order bits of the address are commonly connected to all of the 2/n/ cells so that for any given access cycle, each cell will output data stored in the corresponding cell location on the output lines 1 thru p. In the high order, address bits, which are n in number, are directed to a cell decoding block, shown in the figure, which gates only one of the 2/n/ cell's data output to the output bus.

In this manner, the capacitive loading at the output bus is no greater than the maximum capacitive loading at the output of one of the 2/n/ cells. The loading at the output is therefore kept to a minimum and will effectively be independent of the total number of bits on a chip since each cell is connected to the output bus as a separate entity.

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