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Chip Handler Apparatus for Testing Semiconductor Devices

IP.com Disclosure Number: IPCOM000088906D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 87K

Publishing Venue

IBM

Related People

Fromer, M: AUTHOR [+4]

Abstract

The chip handler is designed to handle the fragile chips individually rather than in bulk form. The handler is designed to pick up the chips from the linear device bank or tray 10, carry them to the test station, automatically align the chips to the probes, provide the necessary environment for the electrical test and then sort the chips into further trays 14. Together with a probe, pin electronics and electronic controls 11, this system comprises an electromechanical system for the electrical test of devices in a chip form.

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Chip Handler Apparatus for Testing Semiconductor Devices

The chip handler is designed to handle the fragile chips individually rather than in bulk form. The handler is designed to pick up the chips from the linear device bank or tray 10, carry them to the test station, automatically align the chips to the probes, provide the necessary environment for the electrical test and then sort the chips into further trays 14. Together with a probe, pin electronics and electronic controls 11, this system comprises an electromechanical system for the electrical test of devices in a chip form.

Referring to the figure, the handler includes an input section, a trays 14. Together with a probe, pin electronics and electronic controls 11, this system comprises an electromechanical system for the electrical test of devices in a chip form.

Referring to the figure, the handler includes an input section, a test section, and a sort section. In the input section, chips are placed in trays 10, pads-up, and the trays are loaded on the handler input transport 16 from which the chips are picked up individually and carried to the test station. In the test section, the chips are aligned automatically to the probe, and contact between the chip pads and probe pins takes place for the electrical test. The temperature of the test is controlled during the test operation in the test section. In the sort section, chips are individually carried from the test section and are sorted into one of many available sorts.

The chips are picked up from the trays 10 by the input shuttle vacuum pencil (not shown). This vacuum pencil is equipped with a soft tip to protect the chip from being damaged. The chip is then carried to the test station where it is deposited on the test pencil 18. It is then automatically aligned either opto- electronically or mechanically. After alignment an index upward will bring the chip into proximity to the probe. Automatic Z sense takes place and contact is established between th...