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Incremental Masterslice Part Number Design

IP.com Disclosure Number: IPCOM000088915D
Original Publication Date: 1977-Aug-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 100K

Publishing Venue

IBM

Related People

Fox, BC: AUTHOR [+2]

Abstract

In the design of large-scale-integration masterslices (MS), a unique MS design is required for different density levels, and automated wiring systems require a set of rules for each unique MS design. The problem becomes greater when the density level of circuits on a given MS is variable, depending upon the part number logic flow and the efficiency of the logic partitioning. It is desirable to provide a family of MS sizes which are increments of each other. In this way logic may be mapped onto a larger chip size if the logic cannot be packaged on the smaller chip size. This avoids the need for logic repartitioning.

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Incremental Masterslice Part Number Design

In the design of large-scale-integration masterslices (MS), a unique MS design is required for different density levels, and automated wiring systems require a set of rules for each unique MS design. The problem becomes greater when the density level of circuits on a given MS is variable, depending upon the part number logic flow and the efficiency of the logic partitioning. It is desirable to provide a family of MS sizes which are increments of each other. In this way logic may be mapped onto a larger chip size if the logic cannot be packaged on the smaller chip size. This avoids the need for logic repartitioning.

The incremental structure shown in Fig. 1 comprises a smaller MS, denoted MS #I, and a larger one, denoted MS #II. The concept is extensible to many different chip sizes. In practice, the largest sized MS is coded into the automated wiring system with the boundaries of the smaller MS image. The part number design is partitioned onto a particular MS by means of a partitioning program to derive the MS size and a placement program to place the circuits in the correct MS zone.

The selection of the correct MS region is shown in the flow diagram of Fig. 2. This selection is divided into two classes: one being an estimation from user's logic and the other based upon the number of overflows resulting from an actual part number design. A part number analysis tool examines the MS region preference and the design time requirements to determine whether the MS selection can be implemented from his set of design goals. If the resulting probability of success is too low, the user has the option of permitting the selection of the next increment or to repartition his logic. The part number analysis tool is retried under these new conditions until...