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Phase or Island Isolation Circuit

IP.com Disclosure Number: IPCOM000089010D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 42K

Publishing Venue

IBM

Related People

Parikh, GH: AUTHOR

Abstract

A circuit using power supplies of two islands of a semiconductor chip is provided to selectively isolate one of the islands from, e.g., bipolar driver circuits, when only one of the two islands is operable.

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Phase or Island Isolation Circuit

A circuit using power supplies of two islands of a semiconductor chip is provided to selectively isolate one of the islands from, e.g., bipolar driver circuits, when only one of the two islands is operable.

High density field-effect transistor (FET) memory arrays are often designed by dividing the total array into two sub-arrays or islands. When one of the two islands is found to be inoperative, the other island may be used in a module by providing twice the number of chips. The undesirable capacitive load produced by the inoperative island is isolated from necessary driving circuits by utilizing the illustrated FET circuits coupled to phase driver circuits.

In operation, when both left and right islands are operative or good, transistors T1 and T2 charge node N1, and transistors T4 and T5 charge node N3 to voltage VH less a threshold voltage. When the input pulse at phi input rises, nodes N1 and N3 are bootstrapped by capacitors C1 and C2 through transistors T3 and T6, respectively, causing nodes N2 and N4 to rise to the level of the input pulse at phi input. Select pulses S(L) and S(R) gate the input pulse through the respective phase driver circuits. The voltage VH or each of the voltages VH(L) and VH(R) may be equal to 9.0 volts.

When the left island is operative and the right island is inoperative, the power supplied to the right island, i.e., VH(R) is connected to the semiconductor substrate bias V(SUB), hence VH(R) = V(SUB...