Browse Prior Art Database

Variable Decrementer

IP.com Disclosure Number: IPCOM000089037D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Plant, JW: AUTHOR

Abstract

A variable decrementer is described for use in a digital computer or digital data processor for decrementing a byte-wide (8-bit) field by 1, 2 or 4 quickly and without using the main arithmetic unit (ALU) in the processor. It is instead done by means of a 256 by 4 read-only storage array (ROS).

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Variable Decrementer

A variable decrementer is described for use in a digital computer or digital data processor for decrementing a byte-wide (8-bit) field by 1, 2 or 4 quickly and without using the main arithmetic unit (ALU) in the processor. It is instead done by means of a 256 by 4 read-only storage array (ROS).

The 8-bit value to be decremented is composed of two 4-bit hexadecimal (hex) digits. The initial value is set into registers R1 and R2 the higher order hex digit being set into R1 and the lower order hex digit being set into R2. The higher order hex digit is also set into a further register B1. AND gates 10, 11, 12, 13 and 14 are assumed to be in an enabled condition, and AND gate 15 is assumed to be in a disabled condition. The Y value obtained from register R1 and the X value obtained from register R2 are used to address a 256 by 4 ROS 16. The permanent bit pattern burned into ROS 16 is such that if X is not equal 0, then the 4-bit out~ut value Z is equal to X-1. If, however, X=0, then Z=Y-1.

Assuming X is not equal 0, the R1+R2 value is decremented bY 1 by first applying an S1 pulse to AND gate 14. This sets the Z=X-1 value into a register B2. Shortly thereafter, an S2 pulse is applied to all stages in registers R1 and R2. This sets the unchanged B1 value into R1 and the X-1 value in register B2 into R2. The resulting R1+R2 value is then one less than the previous value.

If a decrement by 2 is desired, then the "DEC BY 2" line is set to a binary one level and the S1 and S2 pulses are again applied. In this case, AND gates 11 and 13 are disabled by the zero output of NOT circuit 17. This locks bit 3 in the R2 register and prevents any change thereof. It also causes a zero value in the bit 3 position of the X field supplied to ROS 16. Assume, for example, that the hex values in R1 and R2 are F (1111) and D (1101). Then the Y and X values are F (1111) an...