Browse Prior Art Database

Support Processor Error Recovery Mechanism

IP.com Disclosure Number: IPCOM000089043D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 4 page(s) / 94K

Publishing Venue

IBM

Related People

Oliver, BL: AUTHOR [+2]

Abstract

An error recovery mechanism is described for a support processor coupled to a main processor for enabling the support processor to recover from most intermittent failures and some solid failures. The mechanism also provides a comprehensive log of conditions existing at the occurrence of each failure. Fig. 1 shows the general environment. The main processor 10 is a large-scale digital computer having the usual main storage, instruction processing and control sections. It communicates with various peripheral input/output (I/O) devices 11 by way of control units 12 and an I/O channel 13 in the customary manner.

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Support Processor Error Recovery Mechanism

An error recovery mechanism is described for a support processor coupled to a main processor for enabling the support processor to recover from most intermittent failures and some solid failures. The mechanism also provides a comprehensive log of conditions existing at the occurrence of each failure. Fig. 1 shows the general environment. The main processor 10 is a large-scale digital computer having the usual main storage, instruction processing and control sections. It communicates with various peripheral input/output (I/O) devices 11 by way of control units 12 and an I/O channel 13 in the customary manner.

The support processor 14 is a minicomputer which supervises the operation of various main processor console devices, such as a floppy disk unit 15, a keyboard and cathode ray tube (CRT) display unit 16 and a printer 17. Communication with the main processor 10 is accomplished by way of an MP (main processor) bus and an MP adapter 18. Communication with devices 15-17 is accomplished by way of a CD (console device) bus and device adapters 19- 21, respectively. This communication is carried out in substantially the same way as is the I/O interface communication between the channel unit 13 and the control units 12, namely, by means of interlocked signal sequences involving address, command, data and status signals, the data being transferred sequentially in a byte-by-byte manner. Adapters 19-21 correspond in function to the I/O interface control units 12. Support processor 14 relieves the main processor 10 of the various background chores associated with this communication mechanism, and provides a very efficient method for connecting the console devices 15-17 to the main processor 10.

Fig. 2 shows the support processor 14 in greater detail. Like the main processor 10 but to a smaller scale, it also includes a storage unit 22, an instruction processing unit 23 and a control unit 24. In the absence of errors, the support processor operations needed for the transfer of data (including status and control information) between the console devices 15-17 and the main processor 10 are controlled by means of the instructions in a control program 25 located in the support processor storage 22. Typically, data is received on one of the MP and CD buses, temporarily stored in data buffers 26 and subsequently transferred out over the other of the MP and CD buses. In the event of an error within the support processor 14 or in the data being supplied thereto by way of the MP or CD bus, the control program 25 is halted and an error and to decide whether a retry of the failed instruction should be attempted. The error recovery program 27 also stores a comprehensive status record for the failure in an error log buffer 28. If a retry attempt is feasible, error recovery program 27 does the necessary preparation and then returns control to the control program 25.

Errors recognized by the support processor 14 i...