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Sidewall Tailoring Using Two Different Reactive Ion Etchants in Succession

IP.com Disclosure Number: IPCOM000089059D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Bartush, TA: AUTHOR [+3]

Abstract

Reactive ion-etched via hole openings through insulator layers having a shallow angle between the wafer plane and top part of the sidewall are required to obtain good metal layer coverage without breaks at the top edges of the via holes. The shallow angle profile is obtained without excessive tapering of the lower part of the sidewall by providing the desired patterned resist layer 1 profile on top of insulating layer 2, which along with conductors 3 is formed on substrate 4. A major portion of the insulating layer is then etched with a first gas plasma, i.e., CF(4), for etching SiO(2) as illustrated in Fig. 1. The remainder of the etch is then completed down to the conductor 3 in a plasma which attacks the resist, such as mixtures of CF(4)-O(2).

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Sidewall Tailoring Using Two Different Reactive Ion Etchants in Succession

Reactive ion-etched via hole openings through insulator layers having a shallow angle between the wafer plane and top part of the sidewall are required to obtain good metal layer coverage without breaks at the top edges of the via holes. The shallow angle profile is obtained without excessive tapering of the lower part of the sidewall by providing the desired patterned resist layer 1 profile on top of insulating layer 2, which along with conductors 3 is formed on substrate
4. A major portion of the insulating layer is then etched with a first gas plasma,
i.e., CF(4), for etching SiO(2) as illustrated in Fig. 1. The remainder of the etch is then completed down to the conductor 3 in a plasma which attacks the resist, such as mixtures of CF(4)-O(2).

The edges of the resist pattern are now etched away to expose the sharp upper edges 5 of the sidewalls. The exposed edges are etched to produce a fillet 6 at the top of the sidewalls, as shown in Fig. 2. Fillet 6 is easily covered by deposited metal while the sidewall taper is minimized so that the insulating layer thickness, t, between adjacent conductors 3 is not appreciably decreased.

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