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Gettering and Reactive Ion Etching to Improve Device Leakages and Yields

IP.com Disclosure Number: IPCOM000089060D
Original Publication Date: 1977-Sep-01
Included in the Prior Art Database: 2005-Mar-04
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Garbarino, PL: AUTHOR [+3]

Abstract

Gettering of unwanted impurities from a semiconductor has successfully been demonstrated many times. Several different gettering techniques have been employed. Pre-oxidation gettering has been shown to be successful in preventing oxide-induced stacking faults. These stacking faults have been shown to create leakages in FET-type devices. They also can cause epitaxial stacking faults which lead to emitter-collector leakages or "pipes".

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Gettering and Reactive Ion Etching to Improve Device Leakages and Yields

Gettering of unwanted impurities from a semiconductor has successfully been demonstrated many times. Several different gettering techniques have been employed. Pre-oxidation gettering has been shown to be successful in preventing oxide-induced stacking faults. These stacking faults have been shown to create leakages in FET-type devices. They also can cause epitaxial stacking faults which lead to emitter-collector leakages or "pipes".

The value of reactive ion etching (RIE) as an effective impurity and defect removal process is shown by the following experiments. Twelve 15 ohm-cm silicon wafers were used. A thin 200 angstrom silicon dioxide layer was grown on each Si wafer using dry O(2). An argon ion implantation (I/I) at 15O KeV with a dose of 6 x 10/15/cm/2/ was utilized for the wafer backside gettering layer.

The wafers were heat-treated at 1000 degrees C for 3 hours in argon. The wafers were divided into four groups A, B, C, D. "A" was the control group, "B" argon I/I damage left in the wafers, "C" argon I/I damage coated with 350 angstroms Si(3)N(4), and "D" argon I/I RIE 1 mu m of silicon. The 200 angstroms SiO(2) is removed, and 5000 angstroms SiO(2) MOS oxide is grown. Table 1 shows the average data from three wafers per group and 509 MOS measurements per wafer. Table I

Group Yield

"A" = 79% Control

"B" = 86% Ar I/I (not removed)

"C" = 96% Ar I/I Si(3)N(4) "cap"

"D" = 93% Ar I/l RIE.

It can be seen from the data of Table I that gettering the initial wafer and removing the impurities by RIE before the growth of the 5000 angstroms SiO(2) MOS layer can improve the wafer yield. It can be seen by group "B" that gettering, but with subsequent processing, can lead to redistribution of the metallics, thus causing some loss in yield. The growth of the 5000 angstroms SiO(2) removed the majority of implant damage, thus releasing the gettered impurities. Group "C" with it...